1. Field
This disclosure relates generally to an out-of-order processor and, more specifically, reducing store-hit-loads in an out-of-order processor.
2. Related Art
A processor that is capable of issuing and executing instructions out-of-order may permit load instructions to be executed ahead of store instructions. Assuming that a real address (RA) of a younger load instruction does not overlap with an RA of an older store instruction, out-of-order execution of the younger load instruction and the older store instruction may provide performance advantages. In a typical program, the likelihood that an RA of a younger load instruction overlaps with an RA of an older store instruction (that executes after the younger load instruction) is relatively low. As is known, a store violation condition (store-hit-load (SHL)) is indicated when an RA of a store instruction hits in a load reorder queue (LRQ) of a load store unit (LSU). That is, when an RA of a newly issued older store instruction matches an RA of a younger load instruction present in the LRQ of the LSU, an SHL is indicated. However, as detection of an SHL typically occurs late in an instruction execution pipeline, recovering from an SHL typically results in a relatively severe penalty on processor performance. For example, recovery from an SHL typically involves invalidating the younger load instruction that caused the SHL and reissuing the younger load instruction, as well as all instructions issued after the older store instruction.
A number of different approaches for addressing an SHL are known. For example, U.S. Pat. No. 5,666,506 (hereinafter “the '506 patent) discloses an apparatus that dynamically controls out-of-order execution of load instructions and store instructions by detecting an SHL and attempting to avoid the pipeline recovery process penalty. The apparatus of the '506 patent permits load and store instructions to issue and execute out-of-order by incorporating a unique store barrier cache that is used to dynamically predict whether or not an SHL is likely to occur. If an SHL is predicted, issuance of instructions to an LSU are restricted until the store instruction has been executed and it is once again safe to proceed with out-of-order execution. As another example, U.S. Pat. No. 5,781,752 (hereinafter “the '752 patent) discloses a predictor circuit that permits advanced execution of instructions (that depend on previous instructions for their data) by predicting dependencies based on previous mis-speculations detected at the final stages of processing. Synchronization of dependent instructions may be facilitated by a table that includes entries created for each instance of potential dependency.